A FPGA Embedded DSP Supporting Parallel Multiple Low Bit-Width Multiply-Accumulate Operations

With the continuous development of big data and hardware computing platforms, deep learning has been substantially applied in many intelligent scenarios. Recent studies have shown that using low bit-width networks inference can effectively improve overall performance accelerator by reducing computational ability requirements while maintaining recognition accuracy accelerator. Among them, convolutional operations such as 8bit 4bit are widely used applications graph recognition. FPGA chip is core key device digital system, due to excellent reconfigurability FPGA, it become one mainstream platforms field The current FPGAs composed higher multipliers need adapt different application requirements, DSP module resources perform operations, which only occupy part multiplier bit-width, thus wasting a large amount on resources. Therefore, this paper proposes architecture compute multiplications parallel, so new realize double multiply-accumulate without adding multipliers, support any combination signed unsigned operations. design based commercial Stratix IV architecture, circuit designed with SMIC 14nm standard CMOS process. experimental results show when calculating same number 4-bit 8-bit resource consumption area improved reduced 43.5% speed increased 48%.